----------------------------------------------------------------------
-- Bit-serial adder unit
-- Stephen West, James Carroll
-- BYU ECEn 620, October 2008
----------------------------------------------------------------------
Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	-- latency 0 clk
entity BitSerialAdd is
	generic(
		word_length:integer:=8;
		code_vector_length:integer:=16;
		system_word_length:integer:=12
	);
	port(
		clk, 
		a_in, 			-- First argument
		b_in, 			-- second argument
		lsb_in  		-- LSB for synch
		: in std_logic;
		add_out, 		-- sum
		lsb_out			--
		: out std_logic
	);
end entity;

architecture BitSerialAdd of BitSerialAdd is
	component FullAdder is
		port(
			a_in, b_in, c_in:in std_logic;
				add_out, c_out: out std_logic
		);
	end component;
	signal carry_reg, c_in, c_out: std_logic;
begin
	--a+~b+(c|lsb)
	--register the carry
	c_in<=carry_reg and not lsb_in;
	add1: FullAdder port map(c_out=>c_out,c_in=>c_in, a_in=>a_in, b_in=>b_in, add_out=>add_out);
	process(clk, carry_reg, c_out)
	begin
		if(clk'event and clk='1') then
			carry_reg<=c_out;
		end if;
	end process;
	lsb_out<=lsb_in;
end architecture;


